The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the inventors hereof, to the extent the work is described in this background section, as well as aspects of the description that do not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted to be prior art against the present disclosure.
Recently, the use of multi-level signaling, such as PAM-4 signaling, has been gaining favor over binary non-return-to-zero (NRZ) signaling in high speed physical layer transceiver circuit applications for transmitting bit streams of digital data. Generally, this is because PAM-4multi-level signaling packs more bits into a given amount of time on a serial channel in comparison to NRZ signaling. Multi-level PAM-4 signaling, thus, is desirable for use in some high data-rate (e.g., 56 Gbps) serial interfaces. High data-rate serial interface standards, however, typically require a PAM-4multi-level voltage-mode driver circuit to satisfy a strict linearity requirement, for example, with respect to voltage levels representing different combinations of bits. To satisfy such a strict linearity requirement, a PAM-4voltage-mode driver circuit, for instance for PAM-4, must have its regulator output voltage maintained at a relatively constant level. Conventionally, the uniformity of output voltage is obtained using a current mode driver or off-chip charge capacitors.